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cy7c64225 usb-to-uart bridge controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-76294 rev. *b revised march 13, 2013 usb-to-uart bridge controller features universal serial bus (usb) integration ? full-speed usb peripheral compliant with usb2.0 specification ? usb-if certified with tid 40001425 ? support for bus-powered and se lf-powered configurations ? 3 endpoints (1 interrupt in, 1 bulk out and 1 bulk in) ? integrated usb transceiver, 1.5 k ? pull-up resistor on d+ line universal asynchronous receiver transmitter (uart) ? baud rate generation (300 to 230400) ? data format: ? 8 data bits ? 1 stop bit ? no parity, even parity or odd parity ? support for parity, overrun and framing errors ? supports flow control using cts,rts,dtr, dsr ? led signals to indicate activity on txd and rxd lines full device operation from a single voltage supply of 3.3 v or 5 v low power consumption in suspend mode ? 225 a at 5 v operating voltage ? 207 a at 3.3 v operating voltage integrated 24 mhz oscillator integrated 3.3 v regulator integrated flash to store device configuration software support for ease of development ? configuration utility to program device parameters such as vid, pid and string descriptors. ? certified cypress vcp driver for windows (8 / 7 / vista / xp) ? support for device drivers for a ndroid, mac, linux, window ce 4.2, 5.0, 6.0 28-pin ssop 10 mm 7.5 mm , rohs compliant package temperature grade ? commercial operating temperature range of 0 c to +70 c figure 1. cy7c64225 block diagram usb transceiver voltage regulator 24mhz oscillator serial interface engine (sie) pll tx buffer rx buffer flash baud rate generator uart controller txd rxd cts rts dtr dsr tx_led rx_led vdd vbus d+ d- gnd vcfg reset wake suspend
cy7c64225 document number: 001-76294 rev. *b page 2 of 19 contents applications ...................................................................... 3 functional overview ........................................................ 3 introduction .................................................................. 3 functional description ..................................................... 3 usb interface .............................................................. 3 uart controller .......................................................... 3 suspend and resume ................................................. 3 wake .......................................................................... 3 reset ........................................................................... 3 activity indicators ........................................................ 3 vcfg .......................................................................... 4 vbus ........................................................................... 4 regulator ..................................................................... 4 oscillator ............... .............. .............. .............. ............ 4 flash ............................................................................ 4 configurations .................................................................. 4 software and driver support ........................................... 4 pin configuration ............................................................. 5 28-pin part pinout description ........... .............. ............ 5 application circuits .......................................................... 6 bus powered design .............. ..................................... 6 bus powered design using external regulator .......... 7 self powered design ........... ........................................ 8 application diagram ......................................................... 9 usb to rs-232 converter ........................................... 9 usb to uart cable with ttl level uart signals .... 10 interfacing cy7c64225 with bus powered microcontrolle r .................................... 11 interfacing cy7c64225 with self powered microcontrol ler .................................... 12 absolute maximum ratings .......................................... 13 operating temperature .................................................. 13 dc electrical characteristics ........................................ 14 dc gpio specifications ............................................ 14 dc full-speed usb specificat ions .......... ............ ..... 14 ordering information ...................................................... 15 ordering code definitions ..... .................................... 15 packaging information ................................................... 16 package diagrams .................................................... 16 thermal impedance .................................................. 16 solder reflow peak temperat ure ............................. 16 acronyms ........................................................................ 17 reference documents .................................................... 17 document conventions ................................................. 17 units of measure ....................................................... 17 glossary .......................................................................... 17 document history page ................................................. 18 sales, solutions, and legal information ...................... 19 worldwide sales and design s upport ......... .............. 19 products .................................................................... 19 psoc solutions ......................................................... 19
cy7c64225 document number: 001-76294 rev. *b page 3 of 19 applications enable usb connectivity in legacy peripherals with uart industrial and metering devices medical devices point of sales (pos) usb-to-uart cables, usb to rs-232 cables functional overview introduction cypress?s usb-to-uart bridge controller enables seamless pc connectivity for peripherals with ua rt interface. it integrates a usb 2.0 full-speed device controller, uart, voltage regulator, oscillator and flash memory for st oring configuration parameters, offering a cost-effective solution. the controller supports bus-powered and self-powered modes, and enables efficient system power management with su spend and remote wake-up signals. it is available in 28-pin ssop package. functional description usb interface the usb-to-uart device supports full-speed usb operation and is compliant with usb 2.0 sp ecification. the integrated usb serial interface engine (sie) and usb transceiver manage the usb protocol and communication. uart controller the usb-to-uart device integrates a uart controller which supports the baud rates of 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 and 230400* with even, odd or no parity. uart flow control usb-to-uart device supports uart hardware flow control using control signal pairs such as rts (request to send) - cts (clear to send) and dtr (data terminal ready) - dsr (data set ready). data flow control is disabled by default. the hardware flow control is optional and can be selected from the host application software. following is the description of flow control signals: cts (input): this signal can pause or resume data transmission over uart interface. data transmission can be stopped by de-asserting the cts signal and the data transmission can resume with cts assertion. the pause and resume operation does not affect data integrity. rts (output): the receive buffer has a watermark level of 80%. once the data in the receive buffer reaches that level, the rts signal is de-asserted indicating the transmitting device to stop data transmission. start of data consumption by application will reduce device data backlog and once it reaches 50% watermark level, rts signal will be asserted to resume data reception. dtr / dsr: dtr / dsr signals are used to establish communication link with the uart. these signals complement each other in the functionality like rts & cts. note: flow control is not suppor ted when operating the device at 230400 baud rate. in applications where hardware fl ow control is desired, the cts, rts, dsr and dtr pins of the transmitting device have to be connected to rts, cts, dtr and dsr pins of usb-to-uart device respectively. in cases where dtr and dsr pins are not available on the transmitting device, the dtr and dsr pins of usb-to-uart device have to be connected. please refer the circuit diagram shown in figure 8 (provide hyperlink to figure 8). suspend and resume the usb-to-uart device drives the suspend pin to logic low and enters into a low power mode whenever the usb bus goes into suspend state. this help s to meet the stringent suspend current requirement of the usb 2. 0 specification, while using the device in bus powered mode. the device will resume from suspend state under any of the following conditions: 1. any activity is detected on the usb bus 2. wake pin is asserted in orde r to generate remote wake-up to the host. wake wake pin is used to generate re mote wake-up signal on the usb bus. remote wake-up signal is sent only if the host enables this feature through set_feature request. support for remote wake-up is intimated to the host from the device through configuration descriptor during the usb enumeration process. usb-to-uart device allows enabling/disabling the remote wake-up feature through the configuration utility cyusbuart. reset a logic high on the reset pin of usb-to-uart device resets the device. activity indicators tx_led pin and rx_led pin are active low and sink a maximum current of 20 ma each.
cy7c64225 document number: 001-76294 rev. *b page 4 of 19 vcfg an active low on the vcfg indicates that the vbus is detected and the device is configured. vbus this pin is used for vbus detection. a series resistor is required on this pin. regulator the usb-to-uart device integrates a 3.3 v voltage regulator which can be powered by the usb bus or an external power supply. oscillator the usb-to-uart device integrat es a 24 mhz oscillator which is used as a reference clock for sie and uart interface. flash the usb-to-uart device integrates a flash to store device parameters such as vid, pi d, product string descriptor, manufacturer string descriptor and power mode (self-powered or bus-powered). please refer ta b l e 1 for the list of configurable parameters. configurations the internal flash can be used to configure the device parameters listed in table 1 . software and driver support cyusbuart configuration utilit y can be used to configure the parameters listed in table 1 . the configuration utility is available for download from http://www.cypress.com/?rid=61047 . the cypress driver allows ex isting com port based applications to communicate via usb to cy press?s usb-to-uart device. the driver serves the following purposes: add uart port to pcs without uart port add an additional uart port to the pc facilitate easy migration for systems which have a free usb port and need an additional uart port the driver is available for download from http://www.cypress. com/?rid=63794 . this driver is whql certified for the default cypres s vid / pid of 0x04b4 / 0x0008. table 1. internal flash default values name default value vid / pid 0x04b4 / 0x0008 manufacturer string descriptor 2012 cypress semiconductor product string descriptor cypress-usb2uart-ver1.0g bus/self powered self remote wake-up enabled max. power (ma) 100
cy7c64225 document number: 001-76294 rev. *b page 5 of 19 pin configuration 28-pin part pinout description the cy7c64225 usb-to-uart bridge device is available in a 28-pin package as shown in figure 2 . the pin description is listed in ta b l e 2 . table 2. 28-pin part pinout (ssop) pin no. name i/o description figure 2. cy7c64225 usb-uart bridge device 1 gnd power ground 2 tx_led output active low, uart tx_led, max current ?20 ma 3 suspend output active low indicates usb is suspended 4 txd output uart data transmit, output 5 dtr output data terminal ready (dtr) pin 6 reset input active high on this pin resets the device 7 vbus input used for vbus monitoring. this pin requires a series resistor when connected to vbus. the recommended values are in the range of 1 k ? ?10 k ? . 8 dsr input data set ready (dsr) pin 13 gnd power usb ground 14 d+ usb usb d+ line 15 d? usb usb d? line 16 v dd power supply voltage (3.3 v or 5 v) 21 cts input clear to send (cts) input, handshake signal 22 wake input active high on this pin, generates remote wake-up signal on the bus 23 rxd input uart data receive, input 24 rts output request to sent (rts) output, hand- shake signal 26 vcfg output active low in dicates vbus is detected and device is configured 27 rx_led output active low, uart rx_led, max current ?20 ma 28 v dd power supply voltage. 3.3 v or 5 v 9 nc nc no connect 10 nc nc no connect 11 nc nc no connect 12 nc nc no connect 17 nc nc no connect 18 nc nc no connect 19 nc nc no connect 20 nc nc no connect 25 nc nc no connect
cy7c64225 document number: 001-76294 rev. *b page 6 of 19 application circuits the following diagrams illustrates typical application schematics circuits. bus powered design the figure below illustrates the usb bus powered design using cy7c64225. the internal voltage regulator provides the 3.3 v required by the internal usb tr ansceiver. the device parameters such as ?power consumption? and ?bus / self powered? in the internal flash can be modified as required by the application, using the configuratio n utility cyusbuart. a 1k series resistor is required for vbus pin of cy7c64225 in this configuration. figure 3. bus powered configuration cy7c64225 1k 0.01uf vdd wakeup 1k 0.01uf vdd 1k 24 24 reset vdd vdd rx_led vcfg tx_led suspend txd rxd rts cts dtr dsr sw1 sw2 gnd gnd vdd vdd vbus d+ d- d+ d- vbus gnd vdd 560 560 560
cy7c64225 document number: 001-76294 rev. *b page 7 of 19 bus powered design using external regulator figure 4 illustrates the use of cy7c64225 in bus powered mode but running at 3.3 v. this design can be adopted when the circuit operating at 3.3 v is desired (r x, tx, rts, cts, dsr, dtr at 3.3 v). this design uses an external 5 v to 3.3 v regulator to supply the 3.3 v to cy7c64225 from vbus. the 3.3 v to cy7c64225 can also be provided from a regulator which is already available on the circuit board, being used for other components on the board. since the circuit is operating at 3. 3 v, a voltage divider is used to provide 3.3 v from vbus of usb port to ?vbus? pin of cy7c64225. figure 4. bus powered design using external regulator cy7c64225 1k 0.01uf vdd wakeup 1k 0.01uf vdd 10k 24 24 reset vdd vdd rx_led vcfg tx_led suspend txd rxd rts cts dtr dsr sw1 sw2 gnd gnd vdd vbus d+ d- d+ d- vbus gnd 5v to 3.3v regulator vbus vbus vdd vdd 560 560 560 20k
cy7c64225 document number: 001-76294 rev. *b page 8 of 19 self powered design figure 5 illustrates the use of cy7c64225 in self powered mode operating at 3.3 v. vdd is obt ained from an external power supply. as shown in figure 5 , a voltage divider circuit is used to provide 3.3 v from vbus of usb port to vbus pin of cy7c64225. a self powered device can draw more current for its operation from external supply during usb active mode as well as suspend mode as this will not affect the operation of the usb. figure 5. self powered design (vdd = 3.3 v) cy7c64225 1k 0.01uf vdd wakeup 1k 0.01uf vdd vdd vdd rx_led vcfg tx_led txd rxd rts cts dtr dsr sw1 sw2 gnd gnd vdd vdd external supply vdd 560 560 560 10k 24 24 vbus d+ d- d+ d- vbus gnd vbus 20k suspend reset * note 1 note 1. replace the voltage divider circuit (10k and 20k re sistors) with 1k series resistor as shown in figure 3 , if 5 v is applied at vdd in this design.
cy7c64225 document number: 001-76294 rev. *b page 9 of 19 application diagram usb to rs-232 converter in this example the procedure of using the cy7c64225 as a usb to rs-232 converter is illustrat ed. in this application, a ttl to rs232 level converter ic is used on the serial uart interface of the cy7c74225 to convert the ttl levels of the cy7c64225 to rs-232 levels. rs-232 follows bipolar signaling i.e. the output signal toggles between negative an d positive polarity. in rs-232, logic 1 is called mark and is a ?3 v input and logic 0 is called space and is a +3 v input. the output voltage level of rs-232 is +/-5 v to +/-15 v. so there is not only an inversion in polarity but also voltage level translation between the cy7c64225 uart interface and rs-232 signaling. so, rs-232 line driver/receiver is used for providing the necessary polarity inversion and level translation. the connection between cy7c64225 and the rs-232 line driver/receiver is simple. the input lines (dsr, cts and rx) of the uart interface should be connected to the logic outputs of the rs-232 line driver/receiver chip. the output lines (dtr, rts and tx) of the uart interface sh ould be connected to the logic inputs of the rs-232 line driver/receiver chip. the inverted, level-translated uart output will be sent through the line driver pins of the rs-232. figure 6. usb to rs-2 32 converter configuration cy7c64225 1k 0.01uf vdd wakeup 1k 0.01uf vdd 1k 24 24 reset vdd vdd rx_led vcfg tx_led suspend txd rxd rts cts dtr dsr level translator rx_1 tx_1 cts_1 rts_1 dsr_1 dtr_1 sw1 sw2 gnd gnd vdd vdd vbus d+ d- d+ d- vbus gnd vdd 560 560 560 tx_1 rx_1 rts_1 cts_1 dtr_1 dsr_1 db9 male connector
cy7c64225 document number: 001-76294 rev. *b page 10 of 19 usb to uart cable with ttl level uart signals this example illustrates a usb to uart cable design with ttl lev el uart signals using cy7c64225. this design is based on bus powered configuration. figure 7. usb to uart cabl e with ttl level uart signals cy7c64225 1k 0.01uf vdd wakeup 1k 0.01uf vdd 1k 24 24 reset vdd vdd rx_led vcfg tx_led suspend txd rxd rts cts dtr dsr sw1 sw2 gnd gnd vdd vdd vbus d+ d- d+ d- vbus gnd vdd 560 560 560 1k 1k 1k 10k vdd single row header
cy7c64225 document number: 001-76294 rev. *b page 11 of 19 interfacing cy7c64225 with bus powered microcontroller in this scenario both cy7c64225 and the microcontroller (mcu) are powered from vbus. when the microcontroller and cy7c64225 controller are powered from different sources, 1k re sistors are required on rxd and cts lines of cy7c64225. figure 8. interfacing cy7c64225 with bus powered microcontroller cy7c64225 1k wakeup 1k 1k 24 24 reset vdd vdd rx_led vcfg tx_led suspend txd rxd rts cts gnd gnd vbus vbus d+ d- d+ d- vbus gnd mcu vbus rxd txd rts cts usb connector 1k 1k vbus dtr dsr
cy7c64225 document number: 001-76294 rev. *b page 12 of 19 interfacing cy7c64225 with self powered microcontroller in this scenario cy7c64225 is powered from vbus and the microcontroller is powered from an external supply. if both cy7c64225 and the microcontroller (mcu) are operating at 3.3 v, connect a divider circuit to provide 3.3 v to vbus pin of cy7c64225 from vbus pin of usb port. figure 9. interfacing cy7c64225 with self powered microcontroller cy7c64225 1k wakeup 1k 1k 24 24 reset vdd vdd rx_led vcfg tx_led suspend txd rxd rts cts gnd gnd vbus vbus d+ d- d+ d- vbus gnd mcu vdd_5v rxd txd rts cts usb connector 1k 1k vbus dtr dsr
cy7c64225 document number: 001-76294 rev. *b page 13 of 19 absolute maximum ratings operating temperature table 3. absolute maximum ratings parameter description min typ max unit notes t stg storage temperature ?55 ? +100 c higher storage temperatures reduces data retention time. t baketemp bake temperature ? 125 see package label c ? t baketime bake time see package label ? 72 hours ? t a ambient temperature with power applied 0?+70c? v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v ? v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v ? i mio maximum current into any port pin ?25 ? +50 ma ? esd electrostatic discharge voltage ? ? 2000 v human body model esd. flash enpb flash endurance (per block) 50,000 [1] ? ? ? erase/write cycles per block. flash ent flash endurance (total) [2] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years ? table 4. operating temperature parameter description min typ max unit notes t ac commercial ambient temperature 0?+70c? t j junction temperature ?40 ? +100 c the temperature rise from ambient to junction is package specific. see thermal impedance on page 16 . the user must limit the power consumption to comply with this requirement. notes 2. the 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating within one voltage range. voltag e ranges are 3.0 v to 3.6 v and 4.75 v to 5.25 v. 3. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maxi mum cycles each (to limit the total number of cycles to 36x5 0,000 and that no single block ever sees more than 50,000 cycles).
cy7c64225 document number: 001-76294 rev. *b page 14 of 19 dc electrical characteristics dc gpio specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and 0 c < t a < 70 c, or 3.15 v to 3.5 v and 0 c < t a < 70 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc full-speed usb specifications the following table lists guaranteed maximum and minimum specif ications for the voltage and temperature ranges when the imo is selected as system clock: 4.75 v to 5.25 v and 0 c < t a < 70 c, or 3.15 v to 3.5 v and 0 c < t a < 70 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc chip level specifications the following table lists guaranteed maximum and minimum specif ications for the voltage and temperature ranges when the imo is selected as system clock: 4.75 v to 5.25 v and 0 c < t a < 70 c, or 3.15 v to 3.5 v and 0 c < t a < 70 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 5. dc gpio specifications parameter description min typ max unit notes v oh high output level v dd ? 1.0 ? ? v i oh = 10 ma, v dd = 4.75 to 5.25 v v ol low output level ? ? 0.75 v i ol = 25 ma, v dd = 4.75 to 5.25 v i oh high-level source current 10 ? ? ma ? i ol low-level sink current 25 ? ? ma ? v il input low level ? ? 0.8 v v dd = 3.15 to 5.25 v v ih input high level 2.1 ? v v dd = 3.15 to 5.25 v table 6. dc full speed (12 mbps) usb specifications parameter description min typ max unit notes usb interface v di differential input sensitivity 0.2 ? ? v | (d+) ? (d?) | v cm differential input common mode range 0.8 ? 2.5 v ? v se single-ended receiver threshold 0.8 ? 2.0 v ? c in transceiver capacitance ? ? 20 pf ? i io high z state data line leakage ?10 ? 10 ? a0 v < v in < 3.3 v. r ext external usb series resistor 23 ? 25 ? in series with each usb pin. v uoh static output high, driven 2.8 ? 3.6 v 15 k ? 5% to ground. internal pull-up enabled. v uohi static output high, idle 2.7 ? 3.6 v 15 k ? 5% to ground. internal pull-up enabled. v uol static output low ? ? 0.3 v 15 k ? 5% to ground. internal pull-up enabled. z o usb driver output impedance 28 ? 44 ? including r ext resistor. v crs d+/d? crossover voltage 1.3 ? 2.0 v? table 7. dc chip-level specifications parameter description min typ max unit notes v dd supply voltage 3.0 ? 5.25 v usb hardware is not functional when v dd is between 3.5 v to 4.35 v i dd5 supply current ? 14 27 ma conditions are v dd = 5.0 v, t a = 25 c i dd3 supply current ? 8 14 ma conditions are v dd = 3.3 v, t a = 25 c i sb sleep (mode) current ? 3 6.5 ? a v dd = 3.3 v, 0 c < t a < 55 c i sbh sleep (mode) current at high temperature. ? 4 25 ? a v dd = 3.3 v, 55 c < t a < 70 c i susp1 usb suspend current ? 225 285 ? a for 5 v operating voltage range i susp2 usb suspend current ? 208 260 ? a for 3.3 v operating voltage range
cy7c64225 document number: 001-76294 rev. *b page 15 of 19 ordering information ordering code definitions package ordering code temperature range 28-pin ssop CY7C64225-28PVXC 0 c to 70 c 28-pin ssop (tape and reel) CY7C64225-28PVXCt 0 c to 70 c - 25 cy 7 c x = t or blank t = tape and reel; blank = bulk temperature grade: c = commercial pb-free package type: pv = ssop pin count: 28 = 28 pins specific product identifier base part number technology code: c = cmos marketing code company id: cy = cypress x c x pv 28 642
cy7c64225 document number: 001-76294 rev. *b page 16 of 19 packaging information this section illustrates the package specification for the cy7c64225, along with the thermal impedance for the package. package diagrams figure 10. 28-pin ssop (210 mi ls) o28.21 package outline, 51-85079 thermal impedance note assumes 2-layer pcb solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. 51-85079 *e table 8. thermal impedance for the package package typical ? ja 28-pin ssop 96 c/w table 9. solder reflow peak temperature package maximum peak temperature time at maximum peak temperature 28-pin ssop 260 c 20 s
cy7c64225 document number: 001-76294 rev. *b page 17 of 19 acronyms the following table lists the acronyms used in this document. reference documents usb 2.0 specification document conventions units of measure glossary acronym description dc direct current gpio general purpose input/output i/o input/output led light emitting diode pc personal computer ssop shrink small outline package uart universal asynchronous receiver / transmitter usb universal serial bus symbol unit of measure c degree celsius k ? kilohm ? a microampere ma milliampere ? ohm % percent s second v volt w watt asynchronous a signal whose data is acknowledged or acte d upon immediately, irrespective of any clock signal. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for i/o operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. flash flash is a type of non-volatile memory used to stor e small amounts of data that must be saved when power is removed. reset an active high signal that is driven into the device. it causes all operations of the cpu to stop and return to a pre-defined state. v dd a name for a power net meaning ?voltage drain? the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning ?voltage source? the most negative power supply signal. virtual com port a usb virtual com port is a so ftware interface that enables applications to access a usb device as if it were a built-in serial port. many usb virtual com-port devices f unction as bridges that convert between usb and rs-232 or other asynchronous serial interfaces. uart a uart or universal asynchronous receiver-transmitter tran slates between parallel bits of data and serial bits.
cy7c64225 document number: 001-76294 rev. *b page 18 of 19 document history page document title: cy7c64225, us b-to-uart bridge controller document number: 001-76294 rev. ecn no. submission date orig. of change description of change ** 3533464 02/23/2012 hbm new data sheet. *a 3571321 05/15/2012 aasi added applicati on circuit diagrams. minor content edits to add clarity. updated dc chip level specifications and table 6 . *b 3931390 03/13/2013 dtnk / nikl updated features . updated figure 1 (cy7c64225 block diagram). updated functional overview (updated introduction ). renamed ?operational details? as functional description and updated the same section, also added sub-sections namely usb interface , uart controller , regulator , oscillator , flash . updated configurations (updated table 1 ). renamed ?driver? as software and driver support and updated the same section. updated application circuits (updated bus powered design (updated figure 3 ), updated bus powered design using external regulator (updated figure 4 ), updated self powered design (updated description and figure 5 )). updated application diagram (updated figure 6 and added sub-sections namely usb to uart cable with ttl level uart signals , interfacing cy7c64225 with bus powered microcontroller , interfacing cy7c64225 with self powered microcontroller ). updated absolute maximum ratings (updated ta b l e 3 ). replaced eeprom with flash in all instances across the document.
document number: 001-76294 rev. *b revised march 13, 2013 page 19 of 19 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c64225 ? cypress semiconductor corporation, 2012-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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